(A) Field of the Invention
The present invention relates to a semiconductor device manufacture method, and more particularly to a method of manufacturing a semiconductor device having very fine transistors.
(B) Related Art
Semiconductor integrated circuit devices are at the stage of higher integration degree and operation speed. Constituent elements of a semiconductor integrated circuit device, MOS transistors, are becoming very fine in accordance with the scaling rules. The gate insulating film becomes thin and the gate length becomes short. The height of the gate electrode is limited.
As the gate length becomes short, carriers can punch through from the source to drain and the short channel effect appears. In order to prevent the short channel effect, extension regions having shallow junctions are formed in intermediate areas between the source/drain regions.
If element isolation is formed by local oxidation of silicon (LOCOS), bird's beaks are formed gradually thickening the oxide film so that an area of an active region and hence an integration degree are limited. In place of LOCOS, shallow trench isolation (STI) has been adopted by which a trench is formed in a substrate and an insulating film is buried in the trench. With STI, the roughness of a substrate surface can be reduced.
As the gate insulating film is thinned, a phenomenon appears which cannot be neglected: impurities in the gate electrode penetrate through the gate insulating film and invade the channel region. As impurities enter the channel region, a threshold voltage of the channel region varies. Among other ions, boron (B) ions implanted into the gate electrode of a p-channel transistor are likely to penetrate through the gate electrode. Impurity penetration is influenced by ion implantation into the gate electrode and the conditions of subsequent heat treatments. Impurity penetration can be mitigated by executing impurity ion implantation into the gate electrode at a low acceleration energy and executing activation annealing in a very short time.
In general, Ion implantation into the gate electrode and ion implantation into the source/drain regions are carried out simualtaneously. At a low acceleration energy, the source/drain regions become shallow. Well forming ion implantation and threshold voltage adjusting ion implantation are performed for an active region. If the source/drain junctions are shallow, these junctions are positioned in the region having an impurity concentration raised by the threshold voltage adjusting ion implantation, so that a junction capacitance increases. An increase in capacitance lowers the operation speed. Further, a shallow junction increases leak current.
FIG. 4A shows an example of the structure of an n-channel MOS transistor. If the conductivity type is reversed, the structure is of a p-channel MOS transistor. An element isolation trench is formed in a surface layer of a silicon substrate 101, and an insulator is buried in the trench to form an element isolation region 102. In an active region defined by the element isolation region 102, p-type impurities are implanted to form a p-type well 103. In a p-type well surface layer, p-type impurity ions are implanted to form a channel region 104 having a higher impurity concentration and adjusted threshold voltage.
The surface of the silicon substrate is thermally oxidized to form a gate insulating film 105, and a poly-silicon layer 106 is deposited on the gate insulating film. The poly-silicon layer and underlying gate insulating film are patterned to form a gate electrode. By using the gate electrode as a mask, n-type impurity ions are implanted to form n-type extension regions 107. A silicon oxide layer is deposited covering the gate electrode. The silicon oxide layer is etched back to form side wall spacers 108 on the gate electrode side walls.
Impurity ions of the n-type are again implanted to form deep source/drain regions 109 and also implanted into the gate electrode at a sufficient impurity concentration. A metal layer of Co or Ni is deposited on the substrate surface by sputtering and form silicide layers 110 on the surfaces of the source/drain regions and on the surface of the gate electrode.
An insulating layer 112 of silicon oxide or the like is deposited covering the gate electrode, and contact holes are formed through the insulating layer. Conductive plugs 114 are embedded in the contact holes.
In the STI forming process, a silicon nitride layer having an underlying silicon oxide layer is used as a stopper layer for chemical mechanical polishing (CMP). In a process of removing the silicon nitride layer and silicon oxide layer, the shoulder 120 of STI is etched slightly. A concave portion 122 is therefore formed at the STI edge in contact with the active region. An existence of this concave portion swells the silicide layer 110 downward, and also the conductive plug 114 may extend lower than the active region surface. If the effective thickness of the source/drain regions becomes thin, leak current is likely to flow through the source/drain junctions.
FIG. 4B shows another structure formed at a lower ion implantation acceleration energy in order to prevent impurities from penetration through the gate insulating film. Ion implantation into the gate electrode is the same as that into the source/drain regions, so that the junction depth of the source/drain regions 109 becomes shallow. Since the threshold voltage adjusting region 104 is formed in the surface layer of the silicon substrate, the impurity concentration is increased.
A pn junction between the source/drain regions 109 and the threshold volatge adjusting region 104 has a large junction capacitance. Since the source/drain region junction is shallow, a distance between the silicide region 110 and the pn junction becomes short and leak current is likely to flow, assuming a constant depth of the silicide region 110. As described above, the shallow source/drain regions result in an increase in capacitance and leak current and a serious obstacle against a circuit operation.
If the silicide region 110 protrudes downward by the influence of the concave portion on the STI region surface and the conductive plug 114 extends lower than the active region surface, the distance between these conductive regions and the pn junction becomes short. This is the main cause of leak current, among others.
A phenomenon called channeling in silicon crystal is known. As Ion implantation is performed into silicon crystal along a particular direction, atoms are implanted deeper than other methods. This phenomenon is due to the structure established in crystal, called “channel”, through which atoms are easy to move.
If silicon crystal is made amorphous, a channel specific to the crystal disappears and the channeling is hindered. There are various proposals for limiting an arrival depth of implanted ionic atoms by making silicon crystal amorphous before ion implantation is performed. For example, it is known that silicon crystal can be made amorphous by implanting ionic Ge which is the same group element as Si. Since Ge is the same group element as that of Si, the electric characteristics are not influenced fundamentally.
Japanese Patent Laid-open Publication No. HEI-9-23003 discloses the following method. After ion implantation for extension regions, side wall spacers are formed. For an n-channel transistor, phosphorus ions are implanted at an acceleration energy of 20 keV to 60 keV and a dose of about 1×1013 cm−3 to 3×1014 cm−3, and for a p-channel transistor, silicon ions are implanted to make silicon preliminarily amorphous for channeling prevention, and thereafter boron ions are implanted at an acceleration energy of 10 keV to 30 keV and a dose of about 1×1013 cm−3 to 3×1014 cm−3, to thus form deep source/drain regions.
After the deep source/drain regions are formed, silicidation is performed. Thereafter, ion implantation is further executed to increase the impurity concentration of a region under the silicide layer and lower parasitic resistance.
Japanese Patent Laid-open Publication No. HEI-10-22503 proposes a suppression of an arrival depth of phosphorus (P) ions. In forming source/drain regions of an n-channel transistor, first As ions are implanted to make silicon crystal preliminarily amorphous and the P ions are implanted to prevent the channeling in the amorphous layer.